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inhibit flip-flop - translation to ρωσικά
WIKIMEDIA DISAMBIGUATION PAGE
Flipflop; Flip-Flop; Flip-flop (disambiguation); Flip flop
inhibit flip-flop
общая лексика
запрещающий триггер
set-reset flip-flop
![serial-in, parallel-out (SIPO) shift register]]](https://commons.wikimedia.org/wiki/Special:FilePath/4 Bit Shift Register 001.svg?width=200 "serial-in, parallel-out (SIPO) shift register]]")
 Symbol.svg?width=200 "A circuit symbol for a positive-edge-triggered JK flip-flop")
![An animation of a SR latch, constructed from a pair of cross-coupled [[NOR gate]]s. Red and black mean logical '1' and '0', respectively.](https://commons.wikimedia.org/wiki/Special:FilePath/R-S mk2.gif?width=200 "An animation of a SR latch, constructed from a pair of cross-coupled [[NOR gate]]s. Red and black mean logical '1' and '0', respectively.")
![NOR]] gates (on right).](https://commons.wikimedia.org/wiki/Special:FilePath/SR (Clocked) Flip-flop Diagram.svg?width=200 "NOR]] gates (on right).")
![SR}} latch constructed from cross-coupled [[NAND gates]].](https://commons.wikimedia.org/wiki/Special:FilePath/SR Flip-flop Diagram.svg?width=200 "SR}} latch constructed from cross-coupled [[NAND gates]].")
![A transparent latch circuit based on [[bipolar junction transistor]]s](https://commons.wikimedia.org/wiki/Special:FilePath/TTL flip-flop.svg?width=200 "A transparent latch circuit based on [[bipolar junction transistor]]s")
.svg?width=200 "A gated D latch based on an SR NOR latch")
![A gated D latch in [[pass transistor logic]], similar to the ones in the CD4042 or the CD74HC75 integrated circuits.](https://commons.wikimedia.org/wiki/Special:FilePath/Multiplexer-based latch using transmission gates.svg?width=200 "A gated D latch in [[pass transistor logic]], similar to the ones in the CD4042 or the CD74HC75 integrated circuits.")
CIRCUIT THAT HAS TWO STABLE STATES AND CAN BE USED TO STORE STATE INFORMATION
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общая лексика
триггер с раздельным входом
setup time
CIRCUIT THAT HAS TWO STABLE STATES AND CAN BE USED TO STORE STATE INFORMATION
Transparent latch; Setup time; JK flip-flop; JK flip flop; Flip flop (electronics); Jk flipflop; T flipflop; Sr flipflop; D flipflop; Flipflop (switch); Sr latch; Latch (electronics); Bistable circuit; Gated latch; Gated D latch; Latch (electronic); SR latch; Flip flop circuit; SR flip-flop; J-k ff; SR Flip Flop; SR Latch; T flip flop; T flip flops; T flip-flops; T flip-flop; JK flip-flops; JK flip flops; D flip-flop; D flip flop; D flip-flops; D flip flops; Sr flip-flop; SR flip-flops; SR flip flops; Set-Reset flip flop; Set-Reset flip flops; Set-Reset flip-flops; Set-Reset flip-flop; Set-Reset latch; Set-Reset latches; SR latches; RS latch; JKFF; SR flip-flop circuit; Flip-flop-flap; Setup Time; D latch; D Latch; Jk ff; Bistable flip-flop; Polarity hold latch; Flip-flop element; R-S latch; SR Latches; Earle latch; Edge-triggered flip-flop; D flip-flip; JK bistable; Digital reset (electronics); Digitally set (electronics); Digital set (electronics); Digitally reset (electronics); Digital set (logic state); Digital reset (logic state); D-type flip-flop
общая лексика
время установления
нефтегазовая промышленность
время схватывания (цементного раствора)
время монтажа (буровой установки)
Ορισμός
SR flip-flop
<hardware> (Or "RS flip-flop") A "set/reset" flip-flop in
which activating the "S" input will switch it to one stable
state and activating the "R" input will switch it to the other
state.
The outputs of a basic SR flip-flop change whenever its R or S
inputs change appropriately. A clocked SR flip-flop has an
extra clock input which enables or disables the other two
inputs. When they are disabled the outputs remain constant.
If we connect two clocked SR flip-flops so that the Q and /Q
outputs of the first, "master" flip-flop drive the S and R
inputs of the second, "slave" flip-flop, and we drive the
slave's clock input with an inverted version of the master's
clock, then we have an edge-triggered RS flip-flop. The
external R and S inputs of this device are latched on one edge
(transition) of the clock (e.g. the falling edge) and the
outputs will only change on the next opposite (rising) edge.
If both R and S inputs are active (when enabled), a {race
condition} occurs and the outputs will be in an indeterminate
state. A JK flip-flop avoids this possibility.
http://play-hookey.com/digital/logic4.html.
(1997-05-15)
Βικιπαίδεια
Flip-flop
Flip-flops are a simple type of footwear in which there is a band between the big toe and the other toes.
Flip-flop may also refer to:
